Physical Design Engineer

Key Responsibilities Lead end‑to‑end physical design (synthesis, floorplanning, P&R, CTS, timing closure, physical verification) with a strong focus on power‑aware implementation.Architect and execute low‑power methodologies using UPF/CPF – from constraint specification and simulation to final sign‑off, covering voltage domains, level shifters, power switches, retention registers, and isolation cells.Drive top‑level SoC integration with low‑power intent: floorplan optimisation for power grids, I/O and macro placement considering IR/EM, and cross‑block timing/power co‑optimisation.Own sign‑off tasks including STA, IR drop/EM, DRC/LVS, and power integrity analysis – ensuring both performance and power targets are met.Collaborate with front‑end, DFT, and PDK teams to refine power‑aware design rules and flows.Develop Tcl/Perl/Python scripts to automate low‑power flow checks, regression testing, and reporting. What You Bring Bachelor’s or Master’s in EE, Microelectronics, or related field – 5+ years of physical design experience (part‑time candidates with equivalent cumulative track record are welcome).Expertise in Synopsys/Cadence EDA tools (DC, ICC2/Fusion Compiler, Innovus, PrimeTime) with proven ability to handle complex, power‑sensitive designs.Deep, hands‑on experience with UPF/CPF – you have successfully taped out multiple chips using advanced low‑power techniques (power gating, dynamic voltage/frequency scaling, adaptive body biasing, etc.).Strong understanding of the interplay between low‑power intent and physical implementation: you know how to optimise clock trees, placement, and routing for minimal dynamic/leakage power without compromising timing.Scripting proficiency (Tcl/Perl/Python) for flow automation and power‑report parsing.Bonus: Experience in SoC top‑level low‑power integration, chip‑level IR/EM sign‑off, or advanced‑node (7nm/5nm) low‑power challenges.Excellent communication and collaborative problem‑solving skills – you proactively drive power closure and mentor others in UPF/CPF best practices.