Lead Analog IC Layout Engineer

We are seeking a highly skilled and experienced Lead Analog IC Layout Engineer to join our dynamic team in Munich and to lead top-level chip planning and perform block-level custom layouts for CMOS and BiCMOS circuits in planar processes. You will be responsible for contractor based in Asia and India and must have previous experience guiding contractors. You will also play a key role in mentoring junior engineers and contribute to the development of standardized layout methodologies. This is an excellent opportunity for a seasoned professional with lead experience and a strong people skills to make a significant impact in a collaborative and innovative environment. This role is fulltime on site in Munich and applications from across the EU will be considered if the applicant has a pre-existing work permit for Germany. (no visa sponsorship) As a Lead Analog IC Layout Engineer, your key responsibilities will include: Leading top-level chip planning and performing functional-block-level, block-level, sub-block-level, and leaf cell custom layouts for CMOS and BiCMOS circuitsConducting schematic-driven layouts and adhering to design constraintsDesigning die-area efficient layouts based on circuit designer requirementsPerforming floor-planning, power line planning, shielding, and device-matching layoutsVerifying layouts and ensuring compliance with DRC, LVS, and ERC standardsContributing to chip-level routing, layout needs, integration, verification, and tape-out processesCollaborating with local and global design and layout teams across multiple time zonesTraining and mentoring junior layout engineers and offshore layout contractorsDeveloping and implementing standard layout methodologies and workflows across sitesBuilding processes and procedures to achieve high-quality layoutsSupporting additional projects as assigned by management Qualifications And Experience Industry degree in Microelectronics Engineering, BSc or higher8+ years of experience in layout design for analog and full-custom digital blocks, IP Layout is not sufficientProficiency in TSMC 65nm, 55nm, 28nm and 22nm process technologiesAdvanced skills in using layout editing tools within the Cadence Virtuoso design environmentStrong knowledge of debugging DRC/LVS/ERC using Cadence PVS or Mentor CalibreConceptual understanding of layout topics such as parasitics, matching, crosstalk, transistor layout-dependent effects, latch-up, IR drop, electro-migration (EM), and deep N-well and NTN isolationProven ability to solve device matching, electro-migration, signal integrity, and power distribution challenges while adhering to area constraintsExperience in chip-level floor planning, analog block integration, and tape-out processes Only candidates with an existing work permit for Germany will be consider. If you are interested in this opportunity, please contact Ane @ IC Resources with your CV and a time for an initial call.