RTL Engineer

Densityai β€” United States Β· Posted ~3 hours ago

Skills

RTL Design SystemVerilog Digital Design Microarchitecture Synthesis Timing Analysis RTL STA CDC

πŸ”“ Log in to save this job, tailor your resume & track your apply process β€” 7 days free, no card needed.

Log in to add to target list

Summary ✨ AI‑Generated

A semiconductor technology company is seeking an RTL Engineer to design digital blocks for advanced computing hardware. The role covers architecture, implementation, verification collaboration, and silicon readiness.

Highlights

Opportunity to design advanced hardware architectures and contribute to high-performance computing systems.

Description

About The Role Design the RTL that defines our AI accelerator. You'll architect and implement the digital blocks β€” compute datapath, memory subsystem, on-chip interconnect, and control logic β€” from microarchitecture spec through synthesis-ready, timing-clean RTL, and own those blocks end-to-end with architecture, DV, physical design, and DFT all the way to silicon. What You'll Do: Own RTL design of digital blocks/subsystems for our accelerator β€” microarchitecture definition, SystemVerilog implementation, and integrationTranslate architectural specs into efficient, synthesizable RTL that meets power/performance/area (PPA) targetsDrive microarchitecture trade-offs β€” pipelining, datapath vs. control, clock/power gating β€” for high-performance, low-power designPartner with DV on verification, PD on synthesis/timing/floorplan closure, and DFT on testabilityOwn block-level quality: synthesis, timing/constraints (SDC, STA), lint, and CDC signoffContribute to architecture definition and design reviews; debug across simulation, emulation, and post-silicon bring-upUse and develop AI-assisted tool flows to accelerate design and verification What We're Looking For Strong digital-design fundamentals and expert Verilog/SystemVerilog RTL5+ years designing complex digital blocks/SoCs taken to siliconSolid microarchitecture skills β€” pipelining, datapath/control, FIFOs, arbitration, memory subsystems, on-chip interconnect/NoCSynthesis & timing awareness β€” writing synthesizable RTL, SDC constraints, STA, clock/power gating, CDC, lintDemonstrated collaboration with DV, PD, and DFT across the full RTL2GDS flow to tapeoutScripting (Python/Tcl/) for design automation(Optional) AI/ML accelerator or high-performance compute-datapath design; low-power techniques (UPF); high-speed interfaces (HBM, PCIe, SerDes); advanced nodes (7nm or better); RISC-V/CPU design; FPGA prototyping Compensation Final offers depend on level, location, and skills relevant to the role. Additional compensation: equity grant per company guidelines; medical / dental / vision; 401(k); standard PTO. Visa Sponsorship DensityAI sponsors qualified candidates for H-1B, O-1, TN, E-3, and other employment-based visas, and we welcome applicants on F-1 OPT and STEM-OPT. Work authorization is required at start; we provide immigration support to secure or transfer status. Export Controls Aspects of this role may involve access to information subject to U.S. export controls (EAR/ITAR). We may discuss licensing or scope adjustments during the interview. Equal Opportunity DensityAI is an Equal Opportunity Employer. We do not discriminate on the basis of race, color, religious creed, national origin, ancestry, physical or mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, age (40+), sexual orientation, military or veteran status, pregnancy, or any other status protected by law. We comply with the California CROWN Act and provide reasonable accommodations on request. Full compensation packages are based on candidate experience and relevant certifications. California pay range: $215,000 USD - $300,000 USD Compensation Final offers depend on level, location, and skills relevant to the role. Additional compensation: equity grant per company guidelines; medical / dental / vision; 401(k); standard PTO. Visa Sponsorship DensityAI sponsors qualified candidates for H-1B, O-1, TN, E-3, and other employment-based visas, and we welcome applicants on F-1 OPT and STEM-OPT. Work authorization is required at start; we provide immigration support to secure or transfer status. Export Controls Aspects of this role may involve access to information subject to U.S. export controls (EAR/ITAR). We may discuss licensing or scope adjustments during the interview. Equal Opportunity DensityAI is an Equal Opportunity Employer. We do not discriminate on the basis of race, color, religious creed, national origin, ancestry, physical or mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, age (40+), sexual orientation, military or veteran status, pregnancy, or any other status protected by law. We comply with the California CROWN Act and provide reasonable accommodations on request.