Senior Design Verification Engineer

Icresources — United Kingdom · Posted ~2 hours ago

Senior Visa History ✓

Skills

Hardware verification GPU verification UVM Testbench development Functional coverage Assertions SystemVerilog

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Summary ✨ AI‑Generated

A hardware verification role focused on developing verification environments, creating test strategies, and ensuring quality of advanced semiconductor designs.

Highlights

Opportunity to work on advanced hardware verification projects involving next-generation processor technologies.

Description

I am seeking a GPU Verification Engineer to join my clients growing GPU Division. This position is a unique opportunity to exercise your hardware verification skills on cutting edge designs within their prestigious Graphics group. Here you will exercise your skills on key components that meet latest demands and improvements for graphics, AI or connectivity processor and related IP. You will get the chance to work for a powerhouse whereby you will spend your time creating the graphics and AI chips that are at the core of your favourite electronic products. You will: Be responsible for the delivery of all verification activities related to a GPU component or sub-system from early stages of verification planning to sign-offCreate verification plans, develop and maintain UVM testbench componentsParticipate in all stages of design specification definition providing feedback from the verification perspectiveDevelop testbenches in UVM, write tests, sequences, functional coverage, assertions & verification plansBe responsible for the definition, effort estimation and tracking of your own workBe able to influence and advance our GPU verification methodologyHave the opportunity to lead, coach and mentor other members of the teamParticipate in design and verification reviews and recommend improvements Qualifications Have a proven track record of developing verification environments for complex RTL designsHave excellent understanding of constrained-random verification methodology and challenges of verification closureBe confident in defining verification requirements, and work out the implementation approach and details of a testbenchBe able to do root-cause analysis of complex issues and resolve them in a timely mannerHave excellent knowledge of SystemVerilog and UVMBe able to develop new verification flows For more information and a confidential discussion on this superb opportunity contact Rachel Mason at IC Resources.