FPGA Design Engineer

Resquant — Poland · Posted ~2 hours ago

Full-time 22000-31000 PLN gross/month

Skills

FPGA RTL ASIC development digital hardware design hardware security cryptography ASIC

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Summary ✨ AI‑Generated

Join an ambitious deep-tech engineering team developing next-generation secure hardware. As an FPGA Design Engineer, you will implement RTL at block and subsystem level and contribute to advanced FPGA and ASIC development for high-security applications. The role offers exposure to cutting-edge cryptography, semiconductor engineering, secure architecture, and emerging post-quantum technologies in a rapidly growing environment.

Highlights

Strong compensation, an early-stage growth environment, work on cutting-edge hardware security and cryptography, and exposure to advanced FPGA and ASIC engineering.

Description

Resquant is a rapidly growing deep-tech startup focused on next-generation chip security and quantum-resistant cryptography solutions for dual-use and high-security applications. We develop advanced hardware security technologies designed to address emerging threats in post-quantum computing environments, working at the intersection of cryptography, semiconductor engineering, and secure system architecture. We are building a team of highly skilled engineers passionate about cutting-edge FPGA and ASIC development, secure hardware design, and innovative defense-grade technologies. Position: FPGA Design Engineer Compensation: 22,000–31,000 PLN gross/month Employment type: Polish employment contract Resquant is looking for highly skilled FPGA Design Engineers. This is a great opportunity to join a rapidly growing startup at an early stage, working on the latest trends in chip security and cryptography. Main responsibilities: Developing and implementing RTL at block and subsystem level for quantum resistant cryptographic algorithms and cryptographic processors.Defining micro-architecture, performing simulations, and synthesizing digital design.Top-level architecture modeling and integration with 3rd party IP (e.g. RISC-V).Tuning up countermeasures against side-channel attacks. Preparing input for verification environment for FPGAs and ASICs.Participation in certification and technical documentation development.Cooperation with ASIC backend team Our requirements: Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field 5+ years (Mid-level) or 8+ years for Senior-level of hands-on experience in FPGA design and development. Proficient in any VHDL/Verilog/SystemVerilog for RTL design. Knowledge of ASIC design process. Experience with timing analysis, synthesis, and implementation workflows. Experience with high-speed interfaces and protocols such as PCIe, Ethernet, AXI. Knowledge of system integration, including embedded processors. Ability to work independently or strong cooperation skills to work within a cross-functional team. Strong problem-solving and analytical thinking skills. EU citizenship. Preferred candidates with: Knowledge in the field of cryptography. Experience in side-channel attacks and countermeasures. Experience with space technologies and requirements. EU/NATO security clearance. What do we offer: Full time Senior and Mid positionsParticipation in projects aimed at providing backbone for chip security for dual-use markets. Flexible working hours. Ability to work remotely (Hybrid/Full). Equity options. Broad Technical Ownership. Innovation and Cutting-Edge Projects. Opportunity to attend closed events with military representatives.