Senior Verification Engineer

We are seeking a highly skilled and experienced Senior Verification Engineer to join this innovative team. This role offers a unique opportunity to work on advanced verification methodologies and collaborate with a multidisciplinary team of engineers. If you are passionate about verification and thrive in a fast-paced, collaborative environment, we encourage you to apply. Your Responsibilities As a Senior Verification Engineer Will Include Developing SystemVerilog Real Number Modeling (SV-RNM) models for analog and mixed-signal circuits.Creating comprehensive verification plans based on chip or block specifications.Building UVM-based verification environments, including scoreboards, monitors, and sequencers.Conducting digital-top verification using SystemVerilog.Defining and implementing SystemVerilog Assertions (SVA).Collaborating with cross-functional teams, including design, test, and verification engineers, to ensure efficient communication and idea exchange. Qualifications Master’s degree 5+ years industry experience in the Functional verification in the Semiconductor industry.Proficiency in SystemVerilog and Object-Oriented Programming (OOP) principles.Expertise in UVM-based verification methodologies.Strong experience in writing SystemVerilog Assertions (SVA).Fluency in scripting languages such as Perl or Python.Experience generating functional models for analog blocks using SystemVerilog RNM, Wreal (V-AMS), or similar techniques.Familiarity with UVM-AMS methodology. For more information and an initial conversation please contact Ane @ IC Resources with your CV!