ASIC Back-End / Physical Design Engineer

Resquant is a rapidly growing deep-tech startup focused on next-generation chip security and quantum-resistant cryptography solutions for dual-use and high-security applications. We develop advanced hardware security technologies designed to address emerging threats in post-quantum computing environments, working at the intersection of cryptography, semiconductor engineering, and secure system architecture. We are building a team of highly skilled engineers passionate about cutting-edge FPGA and ASIC development, secure hardware design, and innovative defense-grade technologies. Position: ASIC Back-End / Physical Design Engineer (multiple) Compensation: 22,000–33,000 PLN gross/month Employment type: Polish employment contract Resquant is looking for highly skilled ASIC Back-End / Physical Design Engineers for various positions. This is a great opportunity to join a rapidly growing startup at an early stage, working on the latest trends in chip security and cryptography. The project targets the GlobalFoundries 22 nm FDX (22FDX) FD-SOI platform. Main responsibilities: Driving the full physical implementation flow — floorplanning, placement, clock tree synthesis (CTS), and routing — for quantum-resistant cryptographic processors.Performing timing closure and static timing analysis (STA) signoff across multiple corners and modes (setup/hold).Power planning and analysis, including IR-drop and electromigration (EM) checks.Implementing low-power architectures: power domains, level shifters, isolation cells, and the body-bias distribution network required for Adaptive Body Bias (ABB) on GF 22FDX FD-SOI.Handling synthesis-to-layout handoff, ECOs, and tapeout preparation in cooperation with the foundry (GlobalFoundries).Participation in certification and technical documentation development. Our requirements: Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, or a related field.5+ years (Mid-level) or 8+ years (Senior-level) of hands-on experience in ASIC back-end / physical design.Experience with place-and-route tools (e.g. Innovus, IC Compiler II / Fusion Compiler).Strong static timing analysis skills and signoff experience (e.g. PrimeTime, Tempus).Experience with physical verification tools (e.g. Calibre, IC Validator, Pegasus) for DRC/LVS.Proficiency in floorplanning, clock tree synthesis, power planning, and routing.Knowledge of low-power implementation and power intent (UPF/CPF).Understanding of the full ASIC design flow and front-end / back-end interaction.Familiarity with high-speed interfaces and protocols such as PCIe, Ethernet, and AXI.Ability to work independently or strong cooperation skills to work within a cross-functional team.Strong problem-solving and analytical thinking skills.EU citizenship.Candidates must be eligible for employment under a Polish employment contract (UoP). Preferred candidates with: Hands-on experience with the GlobalFoundries 22FDX / FD-SOI process technology.Experience with Adaptive Body Bias (ABB) techniques.Proven track record in low-power optimization.Experience with True Random Number Generators (TRNG) or Physically Unclonable Functions (PUF).Experience with side-channel attacks and countermeasures.EU/NATO security clearance. What do we offer: Full-time Senior and Mid-level positionsSalary range: 22,000–33,000 PLN gross/month, depending on experience and seniority.Employment under an employment contractParticipation in projects aimed at providing a backbone for chip security for dual-use markets.Flexible working hours.Ability to work remotely (Hybrid/Full).Equity options.Broad technical ownership.Innovation and cutting-edge projects.Opportunity to attend closed events with military representatives.