Distinguished Formal Verification Engineer

Astera Labs is seeking a Distinguished Engineer, Formal Verification to join our world-class engineering team in San Jose, California. As a hyper-growth leader in AI infrastructure connectivity, we're revolutionizing how data centers handle explosive AI workloads through cutting-edge PCIe Gen 6/7, CXL, Ethernet, UCIe, and UALink technologies. This is a rare opportunity to shape the formal verification strategy across our entire product portfolio while working on the most advanced connectivity solutions powering the AI revolution. In this highly strategic role, you'll serve as Astera Labs' technical authority on formal verification, defining methodologies and best practices that ensure the highest quality standards across all our next-generation connectivity products. You'll work at the intersection of innovation and reliability, leading efforts to catch critical corner-case bugs that traditional verification methods miss, while mentoring a global team of engineers and representing Astera Labs as a thought leader in the formal verification community. This position offers exceptional scope for impact—your work will directly enable the rack-scale AI infrastructure that's transforming cloud computing and enterprise data centers worldwide. Key Responsibilities Strategic Leadership & Methodology DevelopmentDefine and evolve formal verification strategy, methodologies, and best practices across all product lines for PCIe, CXL, Ethernet, UCIe, and UALink protocolsServe as technical authority on formal verification, providing expert guidance to engineering leadership on risk mitigation and design qualityRepresent Astera Labs in industry forums, standards bodies, and technical conferences as a thought leader in formal verificationDrive cross-functional collaboration to influence technical direction across the organizationTechnical Execution & InnovationDevelop detailed formal verification test plans based on design specifications and collaborate with design teams to refine micro-architecture specificationsIdentify key logic components and critical micro-architectural properties essential for ensuring design correctnessImplement formal verification models, abstractions, assertions, and utilize assertion-based model checking to detect corner-case bugsApply complexity reduction techniques using industry-standard EDA tools to achieve proof convergence or sufficient depthDevelop and maintain scripts to enhance FV productivity and streamline verification processesTeam Development & Cross-Functional PartnershipMentor Principal and Lead Engineers across global sites in advanced formal verification techniquesAssist design teams with the implementation of assertions and formal verification testbenches for RTL at unit/block levelsParticipate in design reviews and collaborate with design teams to optimize design quality and performance, power, area (PPA) metrics based on formal analysis feedbackPrepare and deliver customer meetings and executive presentations with minimal supervisionBasic Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field15+ years of experience in formal verification or 18+ years of experience in traditional design verification with significant formal verification specializationStrong proficiency in SystemVerilog/Verilog with deep understanding of hardware design verificationAdvanced scripting abilities with Python or Perl for automation and productivity enhancementProven ability to manage and prioritize multiple high-impact tasks in a dynamic, fast-paced environment with minimal supervisionStrong cross-functional collaboration skills with demonstrated ability to influence technical direction and drive consensusEntrepreneurial mindset with proactive, customer-focused attitude and ability to think and act quickly while maintaining high quality standardsPreferred Qualifications Master's or PhD in Electrical Engineering, Computer Engineering, Computer Science, or Mathematics with focus on formal methods or verificationHands-on experience with formal verification tools such as Synopsys VCFormal and Cadence JasperGoldExperience with both bug hunting and static proof verification techniquesFamiliarity with automating formal verification workflows within a CI/CD environmentDeep knowledge of high-speed serial protocols: PCIe Gen 4/5/6/7, CXL, Ethernet (100G/400G/800G), UCIe, UALinkParticipation in industry standards bodies (PCI-SIG, CXL Consortium, IEEE, UCIe Consortium)Patents or publications in formal verification or hardware verification methodologiesTrack record of recruiting, mentoring, and developing formal verification talent across distributed teams