Summary
✨ AI‑Generated
Join a global semiconductor engineering organization as a Senior Physical Design Engineer and help establish an in-house ASIC implementation capability. You will work across the full RTL-to-GDSII flow, develop robust physical design methodologies, drive timing closure, and collaborate closely with RTL, analog, verification, and product engineering teams on complex digital and mixed-signal designs.
Highlights
Opportunity to help build a physical design team and establish implementation methodologies from the ground up while collaborating across multiple semiconductor engineering disciplines.
Description
Senior Physical Design Engineer - Rijswijk
A major US semiconductor manufacturer is looking for a Senior Physical Design Engineer to help establish and expand its in-house ASIC implementation team, supporting the development of cutting-edge precision timing and mixed-signal semiconductor products.
You will join a highly successful global engineering organisation responsible for the implementation and delivery of complex digital and mixed-signal ASICs.
This is a unique opportunity to play a key role in building physical design methodologies and flows from the ground up, working closely with RTL, analog, verification, and product engineering teams across the full RTL-to-GDSII flow.
The desired applicant for the role of Senior Physical Design Engineer will have strong backend implementation expertise, excellent timing closure knowledge, and experience developing robust physical design methodologies using Cadence tools.
Experience across low-power and mixed-signal designs would be highly advantageous.
Requirements:
Degree / Masters / Doctorate in Electronics, Microelectronics, Physics, Computer Engineering, or a related fieldStrong industry experience delivering complex ASICs through successful tape-outProven expertise across the full RTL-to-GDSII implementation flowFloorplanning, power planning, power grid design, place and route (PnR), clock tree synthesis (CTS), and physical verificationAdvanced Static Timing Analysis (STA), timing closure, timing constraints, and ECO implementationExperience with low-power implementation methodologies and UPFStrong understanding of signal integrity, power integrity, EM/IR analysis, and physical sign-offExperience developing, maintaining, or building Cadence-based physical design flows and methodologies from scratchScripting and automation skills using Tcl, Python, Perl, or Shell scriptingAbility to work closely with front-end, verification, and analog teams to achieve successful silicon delivery
Excellent salaries, benefits, stocks, bonus, and visa sponsorship are all available for the correctly qualified candidate.
Email - jordan.browne@ic-resources.com
Tel - 01189073075
LinkedIn - https://www.linkedin.com/in/jordan-browne-b4a08b20b/
