Power Management Architecture and Performance Modeling Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. The Role AMD's Datacenter Performance Group is seeking an Engineer for Power Management Architecture and Power and Performance Modeling to support the Power Constrained Performance of our industry-leading AI/ML/HPC GPUs. The role will involve contributing to the Perf@Power attainment of a leading generation of our Instinct accelerators, working closely with a cross-functional team that drives key aspects of Perf@Power attainment, including pre-Si modeling, post-Si correlation, workload analysis, PPA target setting and attainment tracking, power/perf roll-ups and reporting, and methodology development. Being passionate about performance and power efficiency, strong analytical skills, and effective communication are key ingredients for success in this role. Key Responsibilities Support power-constrained performance modeling, projections, target setting, and attainment tracking from Concept-exit (pre-Si) to Product launch (post-Si) for AMD Instinct AI/ML/HPC acceleratorsContribute to power management architecture definition across multiple levels, including:Firmware-based power management features (e.g., SMU-driven power/thermal control, power state management)AVFS (Adaptive Voltage and Frequency Scaling) technologies, including RTAVFS, to reduce voltage/frequency margin based on real-time feedbackMicro-architecture level power features (e.g., clock gating, power gating, dynamic voltage/frequency scaling, p-states)Macro-architecture level power features (e.g., power domains, power delivery partitioning, on-die voltage regulation)SoC-level power management and power capping featuresRack-level and Datacenter-level power management and orchestration featuresDevelop and maintain power and performance models to support Cdyn/Leakage/STA/Area trade-off analysis and attainmentCreate state-of-the-art ML-based modeling solutions to improve accuracy, speed, and scalability of power and performance predictions across pre-Si and post-Si stagesExplore and apply advanced ML techniques (e.g., regression, gradient boosting, neural networks) to model power/performance behavior, automate correlation between pre-Si projections and post-Si silicon data, and accelerate workload power analysisCollaborate with product architecture and business unit teams to help define product configurations, capabilities, and P&P targetsWork cross-functionally with SOC architecture, System Design, IP Design, Circuit Design, Foundry team, CAD, Physical Design, Software, Firmware, Power Management, and Post-Si validation teams to support P&P attainmentAssist with power/performance roll-ups and readouts, and help drive awareness of power efficiency improvements across teamsSupport post-Si power/performance debug and calibration of pre-Si models against silicon dataContribute to workload power analysis and help evolve methodologies for key PPA domains Key Qualifications Background in Computer Architecture, Processor/Accelerator development, or Power Management ArchitectureExperience or strong interest in firmware-based power management, AVFS technologies, and power features spanning micro-architecture, macro-architecture, SoC, Rack, and Datacenter levelsExperience or strong interest in power/performance projections, modeling, and optimization at the SoC or system levelFamiliarity with digital logic physical design and power management techniques (clock gating, power gating, V-F curves, p-states, on-die voltage regulation, clock integrity, etc.)Familiarity with post-silicon power/performance debug and model correlation is a plusGood communication skills and ability to collaborate effectively with various engineering teamsFamiliarity with fundamentals of Machine Learning and hands-on experience with model building is a bonus, with interest in developing new, state-of-the-art ML-based modeling solutions for power and performance predictionKnowledge of DL/ML/LLM/MoE workloads will be a bonus Education Bachelor's or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or related field This role is not eligible for visa sponsorship. Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.